1. Field of the Invention
The present invention relates generally to a method for improving the signal strength of light reflected from a buried topographical grating in a semiconductor device or assembly and the resulting semiconductor devices formed thereby. More specifically, the invention relates to an improved method for reducing reflection caused by differences in the refractive index at the interfaces of adjacent layers of two or more layers overlying a topographical substrate grating in a semiconductor device by inserting therebetween a layer of material having a refractive index intermediate the refractive indexes of the previously-adjacent layers of materials to provide greater signal strength to the grating and back to a detector of the stepper.
2. State of the Art
Increased integration and density of modern semiconductor integrated circuits require increasing the accuracy of alignment-based operations and patterning processes. Specifically, resolution and alignment accuracy are basic performance requirements in alignment and exposure apparatuses used in the field of manufacturing semiconductor devices. For example, precise position alignment (i.e., xe2x80x9cmask alignmentxe2x80x9d) is required each time a mask pattern is reduced in size and transferred to a silicon wafer, other substrate of silicon, or other semiconductor material by optical reduction-photolithographic techniques. Likewise, a precise position alignment is required where a laser trimming apparatus is used to cut sections or levels of the semiconductor on a semiconductor device pattern. These requirements, coupled with the ongoing tendency to further miniaturization and higher capacity of semiconductor devices, have demanded further improvements in the resolution and alignment accuracy used in today""s semiconductor manufacturing processes.
During the manufacturing process, movement of the device or expansion and contraction of a device pattern often produces differences between locations resident in a design-based coordinate system of a device pattern (hereinafter xe2x80x9ccoordinate systemxe2x80x9d) and execution according to the coordinate system by an apparatus responsible for a fabrication step, such as a laser trimming apparatus. That is, unless the coordinate system of the device pattern on the silicon wafer coincides with that actually employed by the fabrication apparatus, it is impossible for the fabrication apparatus to properly align itself onto a precise position on the wafer and to carry out patterning, additive, or subtractive steps in the manufacturing process. For example, where a laser trimming apparatus is used to cut a fuse on a device pattern, the misalignment of the laser trimming apparatus results in an improperly-aligned fuse position, a variation which ultimately results in a cutting failure.
To make an operation executed by the fabrication apparatus precisely coincide with the coordinate system, a plurality of alignment marks is typically formed on the device pattern. Each of the alignment marks is constructed of a highly reflective material, such as aluminum, and is surrounded by a field region devoid of reflective material. Alternatively, where alignment is to an underlying layer (e.g. substrate) topography, a layer of reflective material is deposited over a grating that has been etched into the semiconductor substrate.
In conventional alignment methods utilizing the aforementioned alignment marks or reflective layer, the device pattern is scanned with light of varying wavelengths emanating from an alignment apparatus (e.g., a laser beam) along an x- or y- axis of the coordinate system. Variation in the amount of light reflected vertically from the alignment mark or reflective layer is then detected each time the alignment apparatus scans the area overlying an alignment mark or reflective layer. In this manner, the position of each of the alignment marks or a specific area of the reflective layer is detected. Based on the detected coordinates of the alignment marks or reflective layer areas, the position of the fabrication apparatus or device pattern is adjusted so that the fabrication apparatus is positioned precisely at a point that coincides with the coordinate system of the device pattern.
During the manufacturing process, the alignment marks (or reflective layer) are generally covered with one or more layers of light-transmissive materials, such as polysilicon, resist, insulator, and combinations of other suitable and known films. These intervening layered materials create optical interference with the beam of light travelling between the alignment apparatus and the alignment mark during alignment steps in subsequent phases of the fabrication process. Specifically, as light passes through the interface between two thin-film layers of dielectric, non-absorbing materials having different indexes of refraction, reflection of the light passing therethrough increases. This reflective effect increases as the difference between the indexes of refraction between two adjacent layers increases.
Reflection can cause alignment problems by reducing the incident light signal reaching the reflective layer or alignment marks. Additionally, when the light signal is reflected from the reflective layer or the alignment marks back to the alignment apparatus, the strength and resolution of the light signal is further decreased as the signal undergoes additional reflection when it passes through each interface between adjacent layers of overlying material. Several solutions have been proposed in the prior art to solve the above-mentioned problems associated with alignment inaccuracies due to reflection in semiconductor devices. For example, various alignment systems for use with projection (photoresist) exposure apparatus have utilized an alignment light, having a wavelength that is different from that of an exposing light and that is within the visible wavelength region, in order to enable observation of a wafer surface during the alignment procedure.
Another proposed solution involves formation of a transparent anti-reflective film on a top surface of a resist layer and peeling the film after exposure in order to form a fine resist pattern to high dimensional and alignment accuracies. The use of a low index of refraction material as the anti-reflective film results in a reduction of reflected light at the interface between the resist layer and anti-reflective film, thus improving the dimensional accuracy of a resist image. An alternative method requires removal of a portion of a cover film deposited over the alignment marks to eliminate reflection caused by the cover film.
Other proposed approaches have involved modification of an optical system used with the projection exposure apparatus. For instance, U.S. Pat. No. 5,532,871 to Hashimoto et al. discloses a two-wavelength antireflection film consisting of alternately laminated layers of low and intermediate refractive index materials which are applied to the faces of the mirrors and lenses of an optical system.
Although the aforementioned methods eliminate a number of alignment problems which occur as a result of reflection between the layered materials, these methods also possess a number of shortcomings. For example, the inclusion of anti-reflective layers or films is limited to the top surface of the uppermost layer (usually a resist in the case of photolithography processes). While this approach does provide a more defined light signal, it does not necessarily improve overlay accuracy of the geometries which are patterned from level to level during the fabrication process. Other previously-identified methods require specialized fabrication steps (e.g., removal of the portion of film covering the alignment mark) and equipment, which requirements result in increased fabrication costs and production times.
In view of the foregoing limitations, there is a need in the semiconductor art for an improved method of reducing reflection of light caused by changes in the refractive index at the interface(s) of layered materials in a semiconductor device during the alignment step in semiconductor processing and fabrication. More particularly, there is a need for an improved method for reducing the aforementioned reflection in a semiconductor device or assembly having a substrate topographical grating.
The present invention is directed to a method for improving alignment to underlying topography in a semiconductor device or assembly during an alignment step in a semiconductor device fabrication process. The method comprises forming a thin, corrective layer of material between layers of material which would otherwise be mutually adjacent, hereinafter termed xe2x80x9cprocessxe2x80x9d layers for clarity. A xe2x80x9cthinxe2x80x9d layer is any layer of material which is substantially thinner than the adjacent process layers of materials. Process layers comprise layers of material exhibiting differing refractive indexes, which are applied on a planar surface overlying a topographical substrate grating during a semiconductor device fabrication process, and which would normally lie, after application, in mutually adjacent relationship. The thin, corrective layer is selected from a material having an index of refraction which lies between the indexes of refraction of the materials forming the process layers. The thin, corrective layer is deposited at a specific thickness, which varies depending on the wavelength of the light signal being used and the index of refraction of the corrective layer being used, to maximize transmittance of the stepper signal.
In another embodiment, there is disclosed a method for improving the alignment image intensity emanating from an alignment mark or other reflective surface (target indicia), deposited on a topographical substrate grating in a multi-layered semiconductor device, during an alignment process. The method comprises inserting a thin, corrective layer of material at the interface between two or more process layers of material which would otherwise be mutually adjacent. The thin, corrective layer is made of a material having an intermediate index of refraction relative to the indexes of refraction of the materials forming the process layers.
One particular embodiment of the improved method comprises depositing a layer of reflective material over a topographical grating surface of a substrate of the semiconductor device or assembly. A layer of material having a planar surface is formed over the topographical substrate grating surface. A first process layer of material, having a first index of refraction, is then formed over the planar-surfaced layer. A corrective layer is formed over the first process layer and a second process layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an index of refraction that lies between the first index of refraction and the second index of refraction.
Where structures including additional material process layers are involved, the method can further comprise forming a second corrective layer, made from a material having a second intermediate index of refraction, over the second process layer. A third process layer, having a third index of refraction, is then formed over the second corrective layer. The second intermediate index of refraction lies between the third index of refraction and the second index of refraction.
The present method can also be modified to include additional layers of materials comprising refraction modification layers interposed between or above any of the aforementioned process layers. Likewise, any of the aforementioned structures can be further modified by forming an additional layer of material, having the requisite intermediate index of refraction, over an uppermost process layer to further reduce reflection occurring at the interface between the uppermost process layer and air.
The invention is also directed to semiconductor devices formed through the aforementioned methods.